[ Main Menu / Phenom / Core 2 Processors Chart ]
Athlon 64 (Socket 754) | ||||
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AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
(Clawhammer) (64-bit on-Die unbuffered DDR PC2700 mem controller; 4GB max) [cancelled] | 754 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 104mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Athlon 64 2800+ MMX 3DNow! SSE SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) March 30, 2004 - {$178} | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 3000+ MMX 3DNow! SSE SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) December 15, 2003 - {$218} | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 3200+ MMX 3DNow! SSE SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) September 23, 2003 - {$417} | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 3400+ MMX 3DNow! SSE SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) January 6, 2004 - {$417} | 754 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 3700+ MMX 3DNow! SSE SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) June 1, 2004 - {$710} | 754 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 2800+ MMX 3DNow! SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) July, 2004 | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 3000+ MMX 3DNow! SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) July, 2004 - {$218} | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 3200+ MMX 3DNow! SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) July, 2004 - {$278} | 754 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 3400+ MMX 3DNow! SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) July, 2004 - {$417} | 754 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Sempron 2600+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) 2005 | 754 pins 1200MHz (200x6) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 2800+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) 2005 | 754 pins 1400MHz (200x7) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 3000+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) 2005 | 754 pins 1600MHz (200x8) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 3000+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) 2005 | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 3100+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) July 28, 2004 - {$126} | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 3300+ MMX 3DNow! SSE SSE2 (Paris) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) (32-bit only) 1Q 2005 | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.13µm process 118mm² die |
Sempron 2500+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) July 7, 2005 | 754 pins 1400MHz (200x7) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 2600+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) February 15, 2005 | 754 pins 1600MHz (200x8) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) February 15, 2005 | 754 pins 1600MHz (200x8) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) February 15, 2005 | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3100+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) February 15, 2005 | 754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3300+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) April 18, 2005 | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3 (Palermo) (64-bit on-Die unbuffered DDR mem controller) (32-bit only) July 29, 2005 - {$134} | 754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Athlon 64 (Socket 939) | ||||
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AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
(Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) [not released] | 939 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
(Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) [not released] | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 3500+ MMX 3DNow! SSE SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) June 1, 2004 - {$500} | 939 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 3800+ MMX 3DNow! SSE SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) June 1, 2004 - {$720} | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.13µm process 144mm² die |
Athlon 64 4000+ MMX 3DNow! SSE SSE2 (Sledgehammer) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) October 19, 2004 - {$729} | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 106 million 0.13µm process 193mm² die |
Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3 (San Diego) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) ? | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 114 million 0.09µm process 115mm² die |
(Victoria) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) [cancelled] | 939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | ? million 0.09µm process ?mm² die |
Athlon 64 3000+ MMX 3DNow! SSE SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 4Q 2004 | 939 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.09µm process 102mm² die |
Athlon 64 3200+ MMX 3DNow! SSE SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 4Q 2004 | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.09µm process 102mm² die |
Athlon 64 3500+ MMX 3DNow! SSE SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 4Q 2004 | 939 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.09µm process 102mm² die |
(Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) [not released] | 939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 68.5 million 0.09µm process 102mm² die |
Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3 (Venice) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) May, 2005 | 939 pins 1800MHz (200x9) (64-bit dual-pumped bus) ?v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 114 million 0.09µm process ~120mm² die |
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3 (Venice) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) May, 2005 | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) ?v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 114 million 0.09µm process ~120mm² die |
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3 (Venice) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) May, 2005 | 939 pins 2200MHz (200x11) (64-bit dual-pumped bus) ?v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 114 million 0.09µm process ~120mm² die |
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3 (Venice) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) May, 2005 | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) ?v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 114 million 0.09µm process ~120mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3 (Manchester) (128-bit on-Die unbuffered DDR mem controller) (dual core) August 1, 2005 - {$354} | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 939 | 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process ~147mm² die |
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3 (Manchester) (128-bit on-Die unbuffered DDR mem controller) (dual core) May 31, 2005 - {$537} | 939 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket 939 | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process ~147mm² die |
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3 (Manchester) (128-bit on-Die unbuffered DDR mem controller) (dual core) May 31, 2005 - {$803} | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket 939 | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process ~147mm² die |
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3 (Toledo) (128-bit on-Die unbuffered DDR mem controller) (dual core) May 31, 2005 - {$581} | 939 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket 939 | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 233 million 0.09µm process ~199mm² die |
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3 (Toledo) (128-bit on-Die unbuffered DDR mem controller) (dual core) May 31, 2005 - {$1001} | 939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket 939 | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 233 million 0.09µm process ~199mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Sempron 3000+ MMX 3DNow! SSE SSE2 (Palermo) (128-bit on-Die unbuffered DDR mem controller) June, 2006 | 939 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3200+ MMX 3DNow! SSE SSE2 (Palermo) (128-bit on-Die unbuffered DDR mem controller) June, 2006 | 939 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3400+ MMX 3DNow! SSE SSE2 (Palermo) (128-bit on-Die unbuffered DDR mem controller) June, 2006 | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Sempron 3500+ MMX 3DNow! SSE SSE2 (Palermo) (128-bit on-Die unbuffered DDR mem controller) June, 2006 | 939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 77 million 0.09µm process 84mm² die |
Athlon 64 / Phenom (Socket AM2) (NOT compatible with Socket 940 CPUs!) | ||||
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AMD Processors | Natural State | Sockets | L1/L2/L3 Cache (Associativity) | Transistors |
Athlon 64 LE 1600 MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) 2007 | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 LE 1620 MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) 2007 | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 LE 1640 MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) 2008 | 940 pins 2700MHz (200x13.5) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 LE 1660 MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) ? | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) May 23, 2006 | 940 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) May 23, 2006 | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) May 23, 2006 - {$189} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.25v or 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) May 23, 2006 - {$290} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3 (Orleans) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) February 20, 2007 - {$102} | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Athlon 2650e MMX 3DNow! SSE SSE2 SSE3 (Lima) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) November, 2008 | 940 pins 1600MHz (200x8) (64-bit dual-pumped bus) ?v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 0.065µm process ?mm² die |
Athlon 64 3500+ EE MMX 3DNow! SSE SSE2 SSE3 (Lima) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) February 20, 2007 - {$88} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 0.065µm process ?mm² die |
Athlon 64 3800+ EE MMX 3DNow! SSE SSE2 SSE3 (Lima) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) February 20, 2007 - {$93} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 77 million 0.065µm process ?mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$303} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.075v or 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process 183mm² die |
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$328} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.25v or 1.35v or 1.4v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$365} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process 183mm² die |
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$470} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$558} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process 183mm² die |
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$645} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V) (dual core) May 23, 2006 - {$696} | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process 183mm² die |
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (dual core) December 12, 2006 - {$403} | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.25v or 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC5800 mem controller, AMD-V) (dual core) December 12, 2006 - {$485} | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.09µm process 183mm² die |
Athlon 64 X2 5600+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (dual core) December 12, 2006 - {$505} | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (dual core) February 20, 2007 - {$464} | 940 pins 3000MHz (200x15) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon 64 X2 6400+ MMX 3DNow! SSE SSE2 SSE3 (Windsor) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (dual core) 2007 | 940 pins 3200MHz (200x16) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 1MB on-Die unified L2 (16-way exclusive) | 227 million 0.09µm process 235mm² die |
Athlon X2 BE 2300 MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) June 7, 2007 - {$86} | 940 pins 1900MHz (200x9.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon X2 BE 2350 MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) June 7, 2007 - {$91} | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon X2 BE 2400 MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2007 - {$104} | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon X2 3250e MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) November, 2008 | 940 pins 1500MHz (200x7.5) (64-bit dual-pumped bus) ?v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 3600+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) March, 2007 - {$102} | 940 pins 1900MHz (200x9.5) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) December 5, 2006 | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4050e MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2Q 2008 | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2007 | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.325v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) December 5, 2006 2007 - 1.375v | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.35v, 1.375v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4450e MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2Q 2008 | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2008 | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.375v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) December 5, 2006 | 940 pins 2500MHz (200x12.5) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 4850e MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) April 3, 2008 | 940 pins 2500MHz (200x12.5) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) December 5, 2006 | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5050e MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) December 15, 2008 - {$61} | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.25v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2007 | 940 pins 2700MHz (200x13.5) (64-bit dual-pumped bus) 1.375v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 3Q 2008 - {$87} | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5600+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 2008 | 940 pins 2900MHz (200x14.5) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 5800+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 3Q 2008 - {$112} | 940 pins 3000MHz (200x15) (64-bit dual-pumped bus) 1.35v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3 (Brisbane) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V) (dual core) 1H 2008 | 940 pins 3100MHz (200x15.5) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | 154 million 0.065µm process 126mm² die |
(Rana) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (dual core, HT 3.0, DICE) [cancelled] | 940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v | Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) | ? million 0.065µm process ?mm² die |
Athlon X2 7450 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Kuma) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (dual core, HT 3.0, DICE) January 2009 | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) ?v | Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Athlon X2 7550 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Kuma) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (dual core, HT 3.0, DICE) January 2009 | 940 pins 2500MHz (200x12.5) (64-bit dual-pumped bus) ?v | Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Athlon X2 7750 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Kuma) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (dual core, HT 3.0, DICE) December 15, 2008 - {$79} | 940 pins 2700MHz (200x13.5) (64-bit dual-pumped bus) ?v | Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Athlon X2 7850 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Kuma) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (dual core, HT 3.0, DICE) April 28, 2009 - {$69} | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) ?v | Socket AM2+ | 2x 64KB data (2-way) 2x 64KB instruction (2-way) 2x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
AMD Processors | Natural State | Sockets | L1/L2/L3 Cache (Associativity) | Transistors |
Phenom 9500 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) November 19, 2007 - {$251} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom 9600 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) November 19, 2007 - {$283} | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
(Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) [not released] | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) ?v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
(Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) [not released] | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) ?v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8250e MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) May 25, 2009 - {$122} | 940 pins 1900MHz (200x9.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8400 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) March 27, 2008 | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8450e MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) May 25, 2009 - {$122} | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8450 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) April 23, 2008 - {$145} | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8600 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) March 27, 2008 | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8650 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) April 23, 2008 - {$165} | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8750 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) April 23, 2008 - {$195} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X3 8850 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Toliman) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (tri core, HT 3.0, DICE) 3Q 2009 | 940 pins 2500MHz (200x12.5) (64-bit dual-pumped bus) ?v | Socket AM2+ | 3x 64KB data (2-way) 3x 64KB instruction (2-way) 3x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9100e MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) March 27, 2008 | 940 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.15v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9150e MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) July 1, 2008 - {$175} | 940 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.125v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9350e MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) July 1, 2008 - {$195} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.125v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9550 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) March 27, 2008 - {$209} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9650 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) March 27, 2008 - {$215} | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9750 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) March 27, 2008 - {$215} | 940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.25v or 1.3v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9850 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) March 27, 2008 - {$235} | 940 pins 2500MHz (200x12.5) (64-bit dual-pumped bus) 1.25v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
Phenom X4 9950 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Agena) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) July 1, 2008 - {$235} | 940 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.3v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 2MB on-Die shared L3 (32-way) | 463 million 0.065µm process 288mm² die |
(Ridgeback) (128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V) (quad core, HT 3.0, DICE) [deneb for Socket AM2+] | 940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 6MB on-Die shared L3 (32-way) | 758 million 0.045µm process 258mm² die |
Phenom II X4 920 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Deneb) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) January 8, 2009 - {$235} | 940 pins 2800MHz (200x14) (64-bit dual-pumped bus) ?v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 6MB on-Die shared L3 (48-way) | 758 million 0.045µm process 258mm² die |
Phenom II X4 940 MMX 3DNow! SSE SSE2 SSE3 SSE4 (Deneb) (128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V) (quad core, HT 3.0, DICE) January 8, 2009 - {$275} | 940 pins 3000MHz (200x15) (64-bit dual-pumped bus) ?v | Socket AM2+ | 4x 64KB data (2-way) 4x 64KB instruction (2-way) 4x 512KB on-Die unified L2 (16-way exclusive) 6MB on-Die shared L3 (48-way) | 758 million 0.045µm process 258mm² die |
AMD Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) May 23, 2006 | 940 pins 1600MHz (200x8) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) May 23, 2006 - {$77} | 940 pins 1600MHz (200x8) (64-bit dual-pumped bus) 1.25v or 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3200+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max) May 23, 2006 - {$87} | 940 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.25v or 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max) May 23, 2006 - {$97} | 940 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.25v or 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3500+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) May 23, 2006 - {$109} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.25v or 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 128KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3600+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) May 23, 2006 - {$123} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron 3800+ MMX 3DNow! SSE SSE2 SSE3 (Manila) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 2007? - {$108} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.09µm process 103mm² die |
Sempron LE 1100 MMX 3DNow! SSE SSE2 SSE3 (Sparta) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 4Q 2007 - {$37} | 940 pins 1900MHz (200x9.5) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.065µm process ?mm² die |
Sempron LE 1150 MMX 3DNow! SSE SSE2 SSE3 (Sparta) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 4Q 2007 - {$42} | 940 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) | 81 million 0.065µm process ?mm² die |
Sempron LE 1200 MMX 3DNow! SSE SSE2 SSE3 (Sparta) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 4Q 2007 - {$48} | 940 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.065µm process ?mm² die |
Sempron LE 1250 MMX 3DNow! SSE SSE2 SSE3 (Sparta) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 4Q 2007 - {$53} | 940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.065µm process ?mm² die |
Sempron LE 1300 MMX 3DNow! SSE SSE2 SSE3 (Sparta) (128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max) 2008 - {$41} | 940 pins 2300MHz (200x11.5) (64-bit dual-pumped bus) 1.4v | Socket AM2 Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) | 81 million 0.065µm process ?mm² die |
(Spica) (128-bit on-Die unbuffered DDR2 PC6400 mem controller) (HT 3.0, DICE) [cancelled] | 940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v | Socket AM2+ | 64KB data (2-way) 64KB instruction (2-way) ?KB on-Die unified L2 (16-way exclusive) | ? million 0.065µm process ?mm² die |
Core 2 (Socket 775) | ||||
---|---|---|---|---|
Intel Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Celeron D 420 MMX SSE SSE2 SSE3 (Conroe-L) (EM64T, NX bit) June 3, 2007 - {$39} | 1600MHz (200x8) (64-bit quad-pumped bus) ?v | Socket 775 | 32KB data (8-way) 32KB instruction (8-way) 512KB on-Die unified L2 (2-way) | ? million 0.065µm process ?mm² die |
Celeron D 430 MMX SSE SSE2 SSE3 (Conroe-L) (EM64T, NX bit) June 3, 2007 - {$49} | 775 balls 1800MHz (200x9) (64-bit quad-pumped bus) ?v | Socket 775 | 32KB data (8-way) 32KB instruction (8-way) 512KB on-Die unified L2 (2-way) | ? million 0.065µm process ?mm² die |
Celeron D 440 MMX SSE SSE2 SSE3 (Conroe-L) (EM64T, NX bit) June 3, 2007 - {$59} | 775 balls 2000MHz (200x10) (64-bit quad-pumped bus) ?v | Socket 775 | 32KB data (8-way) 32KB instruction (8-way) 512KB on-Die unified L2 (2-way) | ? million 0.065µm process ?mm² die |
Celeron D 450 MMX SSE SSE2 SSE3 (Conroe-L) (EM64T, NX bit) August 31, 2008 - {$53} | 775 balls 2000MHz (200x10) (64-bit quad-pumped bus) ?v | Socket 775 | 32KB data (8-way) 32KB instruction (8-way) 512KB on-Die unified L2 (2-way) | ? million 0.065µm process ?mm² die |
Celeron E1200 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) January 7, 2008 | 775 balls 1600MHz (200x8) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 512KB on-Die shared L2 (2-way) | 0.065µm process 143mm² die |
Celeron E1400 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) 2Q 2008 | 775 balls 2000MHz (200x10) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 512KB on-Die shared L2 (2-way) | 0.065µm process 143mm² die |
Celeron E1500 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) December 1, 2008 - {$53} | 775 balls 2200MHz (200x11) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 512KB on-Die shared L2 (2-way) | 291 million 0.065µm process 143mm² die |
Celeron E1600 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) June 3, 2009 - {$53} | 775 balls 2400MHz (200x12) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 512KB on-Die shared L2 (2-way) | 291 million 0.065µm process 143mm² die |
Celeron E3200 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) September 8, 2009 - {$43} | 775 balls 2400MHz (200x12) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Celeron E3300 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) September 8, 2009 - {$53} | 775 balls 2500MHz (200x12.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Celeron E3400 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) January 17, 2010 - {$53} | 775 balls 2600MHz (200x13) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Celeron E3500 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) August 30, 2010 - {$52} | 775 balls 2700MHz (200x13.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Intel Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Pentium E2140 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) June 3, 2007 - {$74} | 775 balls 1600MHz (200x8) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (4-way) | 291 million 0.065µm process 143mm² die |
Pentium E2160 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) June 3, 2007 - {$84} | 775 balls 1800MHz (200x9) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (4-way) | 291 million 0.065µm process 143mm² die |
Pentium E2180 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) August 27, 2007 - {$84} | 775 balls 2000MHz (200x10) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (4-way) | 291 million 0.065µm process 143mm² die |
Pentium E2200 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) December, 2007 - {$84} | 775 balls 2200MHz (200x11) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (4-way) | 291 million 0.065µm process 143mm² die |
Pentium E2220 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit) March 6, 2008 | 775 balls 2400MHz (200x12) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (4-way) | 291 million 0.065µm process 143mm² die |
Pentium E2210 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) 2Q 2009 | 775 balls 2200MHz (200x11) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 1MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E5200 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) August 31, 2008 - {$84} | 775 balls 2500MHz (200x12.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E5300 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) December 1, 2008 - {$86} | 775 balls 2600MHz (200x13) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E5400 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) January 18, 2009 - {$84} | 775 balls 2700MHz (200x13.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E5500 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) April 19, 2009 - {$75} | 775 balls 2800MHz (200x14) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E5700 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) August 30, 2010 - {$75} | 775 balls 3000MHz (200x15) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E6300 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) May 10, 2009 - {$84} | 775 balls 2800MHz (266x10.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E6500 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) August, 2009 - {$84} | 775 balls 2933MHz (266x11) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E6600 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) January 17, 2010 - {$84} | 775 balls 3066MHz (266x11.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E6700 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) May 31, 2010 - {$86} | 775 balls 3200MHz (266x12) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Pentium E6800 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT) August 30, 2010 - {$86} | 775 balls 3333MHz (266x12.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 228 million 0.045µm process 82mm² die |
Intel Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Core 2 Duo E4300 MMX SSE SSE2 SSE3 (Allendale) (dual core, EM64T, NX bit) January 7, 2007 - ($183} | 775 balls 1800MHz (200x9) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 167 million 0.065µm process 111mm² die |
Core 2 Duo E4400 MMX SSE SSE2 SSE3 (Allendale) (dual core, EM64T, NX bit) April 22, 2007 - {$133} | 775 balls 2000MHz (200x10) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 167 million 0.065µm process 111mm² die |
Core 2 Duo E4500 MMX SSE SSE2 SSE3 (Allendale) (dual core, EM64T, NX bit) July 16, 2007 | 775 balls 2200MHz (200x11) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 167 million 0.065µm process 111mm² die |
Core 2 Duo E4600 MMX SSE SSE2 SSE3 (Allendale) (dual core, EM64T, NX bit) October 22, 2007 | 775 balls 2400MHz (200x12) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 167 million 0.065µm process 111mm² die |
Core 2 Duo E4700 MMX SSE SSE2 SSE3 (Allendale) (dual core, EM64T, NX bit) March 6, 2008 | 775 balls 2600MHz (200x13) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 167 million 0.065µm process 111mm² die |
Core 2 Duo E6300 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 27, 2006 - ($183} | 775 balls 1866MHz (266x7) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6320 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) April 22, 2007 - {$163} | 775 balls 1866MHz (266x7) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6400 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 27, 2006 - ($224} | 775 balls 2133MHz (266x8) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2MB on-Die shared L2 (8-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6420 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) April 22, 2007 - {$183} | 775 balls 2133MHz (266x8) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6540 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 16, 2007 | 775 balls 2333MHz (333x7) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6550 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT, TXT) July 16, 2007 - {$163} | 775 balls 2333MHz (333x7) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6600 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 27, 2006 - ($316} | 775 balls 2400MHz (266x9) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6700 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 27, 2006 - ($530} | 775 balls 2666MHz (266x10) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6750 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT, TXT) July 16, 2007 - {$183} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E6850 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT, TXT) July 16, 2007 - {$266} | 775 balls 3000MHz (333x9) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
Core 2 Duo E7200 MMX SSE SSE2 SSE3 SSE4 (Wolfdale 3M) (dual core, EM64T, NX bit) April, 2008 - {$133} | 775 balls 2533MHz (266x9.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 3MB on-Die shared L2 (12-way) | 228 million 0.045µm process 82mm² die |
Core 2 Duo E7300 MMX SSE SSE2 SSE3 SSE4 (Wolfdale 3M) (dual core, EM64T, NX bit) August 11, 2008 - {$133} | 775 balls 2666MHz (266x10) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 3MB on-Die shared L2 (16-way) | 228 million 0.045µm process 82mm² die |
Core 2 Duo E7400 MMX SSE SSE2 SSE3 SSE4 (Wolfdale 3M) (dual core, EM64T, NX bit) October 20, 2008 - {$133} | 775 balls 2800MHz (266x10.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 3MB on-Die shared L2 (16-way) | 228 million 0.045µm process 82mm² die |
Core 2 Duo E7500 MMX SSE SSE2 SSE3 SSE4 (Wolfdale 3M) (dual core, EM64T, NX bit) January 18, 2009 - {$133} | 775 balls 2933MHz (266x11) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 3MB on-Die shared L2 (16-way) | 228 million 0.045µm process 82mm² die |
Core 2 Duo E7600 MMX SSE SSE2 SSE3 SSE4 (Wolfdale 3M) (dual core, EM64T, NX bit, VT) June 3, 2009 - {$133} | 775 balls 3066MHz (266x11.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 3MB on-Die shared L2 (16-way) | 228 million 0.045µm process 82mm² die |
Core 2 Duo E8190 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit) January 7, 2008 - {$163} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8200 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) January 7, 2008 - {$163} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8300 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) April, 2008 - {$163} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8400 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) January 7, 2008 - {$183} | 775 balls 3000MHz (333x9) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8500 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) January 7, 2008 - {$266} | 775 balls 3166MHz (333x9.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8600 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) August 11, 2008 - {$266} | 775 balls 3333MHz (333x10) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
Core 2 Duo E8700 MMX SSE SSE2 SSE3 SSE4 (Wolfdale) (dual core, EM64T, NX bit, VT, TXT) January 18, 2009 | 775 balls 3500MHz (333x10.5) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | 410 million 0.045µm process 107mm² die |
(Ridgefield) (dual core, EM64T, NX bit, VT) [cancelled] | 775 balls ?MHz (400x?) (64-bit quad-pumped bus) ?v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 6MB on-Die shared L2 (24-way) | ? million 0.045µm process ?mm² die |
Intel Processors | Natural State | Sockets | L1/L2 Cache (Associativity) | Transistors |
Core 2 Extreme X6800 MMX SSE SSE2 SSE3 (Conroe) (dual core, EM64T, NX bit, VT) July 27, 2006 - {$999} | 775 balls 2933MHz (266x11) (64-bit quad-pumped bus) 1.2v | Socket 775 | 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-Die shared L2 (16-way) | 291 million 0.065µm process 143mm² die |
(Kentsfield) (quad core (dual die), EM64T, NX bit, VT) [not released] | 775 balls 2133MHz (266x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Quad Q6600 MMX SSE SSE2 SSE3 (Kentsfield) (quad core (dual die), EM64T, NX bit, VT) January 8, 2007 - {$851} | 775 balls 2400MHz (266x9) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Quad Q6700 MMX SSE SSE2 SSE3 (Kentsfield) (quad core (dual die), EM64T, NX bit, VT) July 16, 2007 - {$530} | 775 balls 2666MHz (266x10) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Extreme QX6700 MMX SSE SSE2 SSE3 (Kentsfield) (quad core (dual die), EM64T, NX bit, VT) November 14, 2006 - {$999} | 775 balls 2666MHz (266x10) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Extreme QX6800 MMX SSE SSE2 SSE3 (Kentsfield) (quad core (dual die), EM64T, NX bit, VT) April 9, 2006 - {$1199} | 775 balls 2933MHz (266x11) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Extreme QX6850 MMX SSE SSE2 SSE3 (Kentsfield) (quad core (dual die), EM64T, NX bit, VT, TXT) July 16, 2007 - {$999} | 775 balls 3000MHz (333x9) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB on-Die shared L2 (16-way) | 582 million 0.065µm process (2) 142mm² die |
Core 2 Quad Q8200 MMX SSE SSE2 SSE3 (Yorkfield) (quad core (dual die), EM64T, NX bit) August 31, 2008 - {$224} | 775 balls 2333MHz (333x7) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 2MB on-Die shared L2 (8-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q8200S MMX SSE SSE2 SSE3 (Yorkfield) (quad core (dual die), EM64T, NX bit) Janury 18, 2009 - {$245} | 775 balls 2333MHz (333x7) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 2MB on-Die shared L2 (8-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q8300 MMX SSE SSE2 SSE3 (Yorkfield) (quad core (dual die), EM64T, NX bit) December 1, 2008 - {$224} | 775 balls 2500MHz (333x7.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 2MB on-Die shared L2 (8-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q8400 MMX SSE SSE2 SSE3 (Yorkfield) (quad core (dual die), EM64T, NX bit) April 19, 2009 - {$183} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 2MB on-Die shared L2 (8-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q8400S MMX SSE SSE2 SSE3 (Yorkfield) (quad core (dual die), EM64T, NX bit) April 19, 2009 - {$245} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 2MB on-Die shared L2 (8-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9300 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) January 7, 2008 - {$266} | 775 balls 2500MHz (333x7.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9400 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) August 11, 2008 - {$266} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9400S MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) January 18, 2009 - {$320} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9450 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) January 7, 2008 - {$316} | 775 balls 2666MHz (333x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9500 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT) January 17, 2010 - {$183} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9505 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT) September 8, 2009 - {$213} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9505S MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) September 8, 2009 - {$277} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 3MB on-Die shared L2 (12-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9550 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) January 7, 2008 - {$530} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9550S MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) January 18, 2009 - {$369} | 775 balls 2833MHz (333x8.5) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Quad Q9650 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT, TXT) August 11, 2008 - {$530} | 775 balls 3000MHz (333x9) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Extreme QX9650 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT) November 11, 2007 - {$999} | 775 balls 3000MHz (333x9) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Extreme QX9770 MMX SSE SSE2 SSE3 SSE4 (Yorkfield) (quad core (dual die), EM64T, NX bit, VT) March 24, 2008 - {$1399} | 775 balls 3200MHz (400x8) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
Core 2 Extreme QX9775 MMX SSE SSE2 SSE3 SSE4 (Harpertown) (quad core (dual die), EM64T, NX bit, VT) February 19, 2008 - {$1499} | 771 balls 3200MHz (400x8) (64-bit quad-pumped bus) ?v | Socket 771 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 6MB on-Die shared L2 (24-way) | 820 million 0.045µm process (2) 107mm² die |
( ? ) (quad core, EM64T, NX bit, VT) [cancelled] | 775 balls ?MHz (?x?) (64-bit quad-pumped bus) ?v | Socket 775 | 4x 32KB data (8-way) 4x 32KB instruction (8-way) 4x ?MB on-Die unified L2 (?-way) | ? million 0.045µm process ?mm² die |