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786 Processors Chart

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This list is not comprehensive.


Athlon (Slot A)
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 500 MMX 3DNow!
(K7)
August 9, 1999 - {$249}		575 pins (242 pin SEC)
500MHz (100x5.0)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.25µm process
184mm² die
Athlon 550 MMX 3DNow!
(K7)
August 9, 1999 - {$449}		575 pins (242 pin SEC)
550MHz (100x5.5)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.25µm process
184mm² die
Athlon 600 MMX 3DNow!
(K7)
August 9, 1999 - {$615}		575 pins (242 pin SEC)
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.25µm process
184mm² die
Athlon 650 MMX 3DNow!
(K7)
August 9, 1999 - {$849}		575 pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.25µm process
184mm² die
Athlon 700 MMX 3DNow!
(K7)
October 4, 1999 - {$849}		575 pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.25µm process
184mm² die
Athlon 550 MMX 3DNow!
(K75)
January 2000		575 pins (242 pin SEC)
550MHz (100x5.5)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 600 MMX 3DNow!
(K75)
January 2000		575 pins (242 pin SEC)
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 650 MMX 3DNow!
(K75)
January 2000		575 pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 700 MMX 3DNow!
(K75)
January 2000		575 pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 750 MMX 3DNow!
(K75)
November 29, 1999 - {$799}		575 pins (242 pin SEC)
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.6v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 800 MMX 3DNow!
(K75)
January 6, 2000 - {$849}		575 pins (242 pin SEC)
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 850 MMX 3DNow!
(K75)
February 11, 2000 - {$849}		575 pins (242 pin SEC)
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 900 MMX 3DNow!
(K75)
March 6, 2000 - {$899}		575 pins (242 pin SEC)
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.8v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 950 MMX 3DNow!
(K75)
March 6, 2000 - {$999}		575 pins (242 pin SEC)
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.8v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 1G MMX 3DNow!
(K75)
March 6, 2000 - {$1299}		575 pins (242 pin SEC)
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.8v/3.3v split		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable		22 million
0.18µm process
102mm² die
Athlon 650 MMX 3DNow!
(Thunderbird)		? pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.7v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 700 MMX 3DNow!
(Thunderbird)		? pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.7v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 750 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$319}		? pins (242 pin SEC)
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.7v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 800 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$359}		? pins (242 pin SEC)
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 850 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$507}		? pins (242 pin SEC)
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 900 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$589}		? pins (242 pin SEC)
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.75v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 950 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$759}		? pins (242 pin SEC)
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.75v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1G MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$990}		? pins (242 pin SEC)
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v		Slot A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon Ultra 1.33G MMX 3DNow!
(Mustang)
[cancelled]		? pins (242 pin SEC)
1333MHz (133x10.0)
(64-bit dual-pumped bus)
?v		Slot A64KB data (2-way)
64KB instruction (2-way)
512KB or
1MB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.18µm process
120+mm² die


Athlon (Socket A)
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Duron 600 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$112}		453 pins
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.5v or 1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 650 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$154}		453 pins
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.5v or 1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 700 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$192}		453 pins
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.5v or 1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 750 MMX 3DNow!
(Spitfire)
September 5, 2000 - {$181}		453 pins
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 800 MMX 3DNow!
(Spitfire)
October 17, 2000 - ($170)		453 pins
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 850 MMX 3DNow!
(Spitfire)
January 8, 2001 - {$149}		453 pins
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 900 MMX 3DNow!
(Spitfire)
April 2, 2001 - {$129}		453 pins
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 950 MMX 3DNow!
(Spitfire)
June 6, 2001 - {$122}		453 pins
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25 million
0.18µm process
100mm² die
Duron 1.0G MMX 3DNow! SSE
(Morgan)
August 20, 2001 - {$89}		453 pins
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25.2 million
0.18µm process
106mm² die
Duron 1.1G MMX 3DNow! SSE
(Morgan)
October 1, 2001 - {$103}		453 pins
1100MHz (100x11.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25.2 million
0.18µm process
106mm² die
Duron 1.2G MMX 3DNow! SSE
(Morgan)
November 15, 2001 - {$103}		453 pins
1200MHz (100x12.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25.2 million
0.18µm process
106mm² die
Duron 1.3G MMX 3DNow! SSE
(Morgan)
January 21, 2002 - {$118}		453 pins
1300MHz (100x13.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		25.2 million
0.18µm process
106mm² die
Duron 1.33G MMX 3DNow! SSE
(Appaloosa)
[cancelled]		453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
?v		Socket A64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.13µm process
?mm² die
Duron 1.4G MMX 3DNow! SSE
(Applebred)
August 2003 - {$32}		453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.5v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.13µm process
?mm² die
Duron 1.6G MMX 3DNow! SSE
(Applebred)
August 2003 - {$39}		453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.5v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.13µm process
?mm² die
Duron 1.8G MMX 3DNow! SSE
(Applebred)
August 2003 - {$47}		453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.5v		Socket A64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.13µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 650 MMX 3DNow!
(Thunderbird)
200x?		453 pins
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.7v or 1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 700 MMX 3DNow!
(Thunderbird)
200x?		453 pins
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.7v or 1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 750 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$319}		453 pins
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.7v or 1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 800 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$359}		453 pins
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v or 1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 850 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$507}		453 pins
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v or 1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 900 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$589}		453 pins
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 950 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$759}		453 pins
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1G MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$990}		453 pins
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$385}		453 pins
1000MHz (133x7.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.1G MMX 3DNow!
(Thunderbird)
August 28, 2000 - {$853}		453 pins
1100MHz (100x11.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.13G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$506}		453 pins
1133MHz (133x8.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.2G MMX 3DNow!
(Thunderbird)
October 17, 2000 - {$612}		453 pins
1200MHz (100x12.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.2G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$673}		453 pins
1200MHz (133x9.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.3G MMX 3DNow!
(Thunderbird)
March 22, 2001 - {$318}		453 pins
1300MHz (100x13.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.33G MMX 3DNow!
(Thunderbird)
March 22, 2001 - {$350}		453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.4G MMX 3DNow!
(Thunderbird)
June 6, 2001 - {$253}		453 pins
1400MHz (100x14.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
Athlon 1.4G MMX 3DNow!
(Thunderbird)
June 6, 2001 - {$253}		453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37 million
0.18µm process
120mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon Ultra 1.33G MMX 3DNow!
(Mustang)
[cancelled]		453 pins
1333MHz (133x10)
(64-bit dual-pumped bus)
?v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB or
1MB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.18µm process
120+mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon MP 1.0G MMX 3DNow! SSE
(Palomino)
June 5, 2001 - {$215}		453 pins
1000MHz (133x7.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 1.2G MMX 3DNow! SSE
(Palomino)
June 5, 2001 - {$265}		453 pins
1200MHz (133x9.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 1500+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$180}		453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 1600+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$210}		453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 1800+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$302}		453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 1900+ MMX 3DNow! SSE
(Palomino)
December 12, 2001 - {$319}		453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 2000+ MMX 3DNow! SSE
(Palomino)
March 13, 2002 - {$415}		453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 2100+ MMX 3DNow! SSE
(Palomino)
June 19, 2002 - {$262}		453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon MP 2000+ MMX 3DNow! SSE
(Thoroughbred)
August 27, 2002		453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
85mm² die
Athlon MP 2200+ MMX 3DNow! SSE
(Thoroughbred)
August 27, 2002 - {$224}		453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
85mm² die
Athlon MP 2400+ MMX 3DNow! SSE
(Thoroughbred)
December 10, 2002 - {$228}		453 pins
2000MHz (133x15.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
85mm² die
Athlon MP 2600+ MMX 3DNow! SSE
(Thoroughbred)
February 4, 2003 - {$273}		453 pins
2133MHz (133x16.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
85mm² die
Athlon MP 2800+ MMX 3DNow! SSE
(Barton MP)
May 6, 2003 - {$275}		453 pins
2133MHz (133x16)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon XP 1500+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$130}		453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 1600+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$160}		453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 1700+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$190}		453 pins
1466MHz (133x11.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 1800+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$252}		453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 1900+ MMX 3DNow! SSE
(Palomino)
November 5, 2001 - {$269}		453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 2000+ MMX 3DNow! SSE
(Palomino)
January 7, 2002 - {$339}		453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 2100+ MMX 3DNow! SSE
(Palomino)
March 13, 2002 - {$420}		453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.75v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.5 million
0.18µm process
128mm² die
Athlon XP 1600+ MMX 3DNow! SSE
(Thoroughbred)
May, 2003		453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
84mm² die (Dec 02)
Athlon XP 1700+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002		453 pins
1466MHz (133x11.0)
(64-bit dual-pumped bus)
1.5v or 1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
84mm² die (Dec 02)
Athlon XP 1800+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002		453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.5v or 1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
84mm² die (Dec 02)
Athlon XP 1900+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002		453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.5v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
Athlon XP 2000+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002		453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.6v or 1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
84mm² die (Dec 02)
Athlon XP 2100+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002		453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
Athlon XP 2200+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002 - {$241}		453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.6v or 1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
81mm² die
84mm² die (Dec 02)
Athlon XP 2400+ MMX 3DNow! SSE
(Thoroughbred)
August 21, 2002 - {$193}		453 pins
2000MHz (133x15.0)
(64-bit dual-pumped bus)
1.6v or 1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Athlon XP 2600+ MMX 3DNow! SSE
(Thoroughbred)
August 21, 2002 - {$297}		453 pins
2133MHz (133x16.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Athlon XP 2600+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002		453 pins
2083MHz (166x12.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Athlon XP 2700+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002 - {$349}		453 pins
2166MHz (166x13.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Athlon XP 2800+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002 - {$397}		453 pins
2250MHz (166x13.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Athlon XP 2000+ MMX 3DNow! SSE
(Thorton)
September, 2003		453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 2200+ MMX 3DNow! SSE
(Thorton)
September, 2003		453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 2400+ MMX 3DNow! SSE
(Thorton)
September, 2003		453 pins
2000MHz (133x15.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 2500+ MMX 3DNow! SSE
(Barton)
February 10, 2003		453 pins
1833MHz (166x11.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 2600+ MMX 3DNow! SSE
(Barton)
May 13, 2003		453 pins
1916MHz (166x11.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 2800+ MMX 3DNow! SSE
(Barton)
February 10, 2003		453 pins
2083MHz (166x12.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 3000+ MMX 3DNow! SSE
(Barton)
February 10, 2003 - {$588}		453 pins
2166MHz (166x13.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 3000+ MMX 3DNow! SSE
(Barton)
May 13, 2003		453 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP 3200+ MMX 3DNow! SSE
(Barton)
May 13, 2003 - {$464}		453 pins
2200MHz (200x11.0)
(64-bit dual-pumped bus)
1.65v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Athlon XP MMX 3DNow! SSE
(Thoroughbred-S)
[cancelled]		453 pins
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket A64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		? million
0.09µm process
50mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Sempron 2200+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$39}		453 pins
1500MHz (166x9.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2300+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$45}		453 pins
1583MHz (166x9.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2400+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$61}		453 pins
1666MHz (166x10.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2500+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$74}		453 pins
1750MHz (166x10.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2600+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$85}		453 pins
1833MHz (166x11.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2800+ MMX 3DNow! SSE
(Thoroughbred)
July 28, 2004 - {$109}		453 pins
2000MHz (166x12.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		37.2 million
0.13µm process
84mm² die
Sempron 2200+ MMX 3DNow! SSE
(Thorton)
August, 2004		453 pins
1500MHz (166x9.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Sempron 2400+ MMX 3DNow! SSE
(Thorton)
December, 2004		453 pins
1666MHz (166x10.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Sempron 2500+ MMX 3DNow! SSE
(Thorton)
December, 2004		453 pins
1750MHz (166x10.5)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Sempron 2600+ MMX 3DNow! SSE
(Thorton)
December, 2004		453 pins
1833MHz (166x11.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Sempron 2800+ MMX 3DNow! SSE
(Thorton)
August, 2004		453 pins
2000MHz (166x12.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die
Sempron 3000+ MMX 3DNow! SSE
(Barton)
September 17, 2004 - {$123}		453 pins
2000MHz (166x12.0)
(64-bit dual-pumped bus)
1.6v		Socket A64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable		54.3 million
0.13µm process
101mm² die


Pentium 4 / Pentium D (Socket 423/478/T)
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Pentium 4 1.3G MMX SSE SSE2
(Willamette)
January 3, 2001 - {$409}		423 pins
1300MHz (100x13)
(64-bit quad-pumped bus)
1.7v or 1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.4G MMX SSE SSE2
(Willamette)
November 20, 2000 - {$644}		423 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v or 1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.5G MMX SSE SSE2
(Willamette)
November 20, 2000 - {$819}		423 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v or 1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.6G MMX SSE SSE2
(Willamette)
July 2, 2001 - {$294}		423 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.7G MMX SSE SSE2
(Willamette)
April 23, 2001 - {$352}		423 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.8G MMX SSE SSE2
(Willamette)
July 2, 2001 - {$562}		423 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.9G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$375}		423 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 2.0G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$562}		423 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.75v		Socket 4238KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.4G MMX SSE SSE2
(Willamette)
September 27, 2001		478 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.5G MMX SSE SSE2
(Willamette)
August 27, 2001		478 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.6G MMX SSE SSE2
(Willamette)
August 27, 2001		478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.7G MMX SSE SSE2
(Willamette)
August 27, 2001		478 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.8G MMX SSE SSE2
(Willamette)
August 27, 2001		478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.9G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$375}		478 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 2.0G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$562}		478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Pentium 4 1.6A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002		478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.5v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 1.8A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002		478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.0A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002		478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.5v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 1.6A MMX SSE SSE2
(Northwood)
January 7, 2002		478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.5v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 1.8A MMX SSE SSE2
(Northwood)
January 7, 2002		478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.0A MMX SSE SSE2
(Northwood)
January 7, 2002 - {$364}		478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.2G MMX SSE SSE2
(Northwood)
January 7, 2002 - {$562}		478 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.26G MMX SSE SSE2
(Northwood)
May 5, 2002 - {$423}		478 pins
2266MHz (133x17)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.4G MMX SSE SSE2
(Northwood)
April 2, 2002 - {$562}		478 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.4B MMX SSE SSE2
(Northwood)
May 5, 2002 - {$562}		478 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (Jul 02)
Pentium 4 2.4C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
May 21, 2003 - {$178}		478 pins
2400MHz (200x12)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.5G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$243}		478 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.53G MMX SSE SSE2
(Northwood)
May 5, 2002 - {$637}		478 pins
2533MHz (133x19)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
146mm² die
131mm² die (May 02)
Pentium 4 2.6G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$401}		478 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.6C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
May 21, 2003 - {$218}		478 pins
2600MHz (200x13)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.67G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$401}		478 pins
2666MHz (133x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.8G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$508}		478 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.8C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
May 21, 2003 - {$278}		478 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 3.0C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
April 14, 2003 - {$417}		478 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525 or 1.55v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 3.06G MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
November 14, 2002 - {$637}		478 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 3.2C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
June 23, 2003 - {$637}		478 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 3.4C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading)
February 2, 2004 - {$417}		478 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Pentium 4 2.26A MMX SSE SSE2 SSE3
(Prescott)
2H 2004		478 pins
2266MHz (133x17)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.4A MMX SSE SSE2 SSE3
(Prescott)
June, 2004		478 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.4E MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
1H 2004		478 pins
2400MHz (200x12)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.8A MMX SSE SSE2 SSE3
(Prescott)
2H 2004		478 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.8A MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
February 2, 2004 - {$178}		478 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.8E MMX SSE SSE2 SSE3
(Prescott)
2H 2004		478 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.8E MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
February 2, 2004 - {$178}		478 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.0E MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
February 2, 2004 - {$218}		478 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.2E MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
February 2, 2004 - {$278}		478 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.4E MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
February 2, 2004 - {$417}		478 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 505 MMX SSE SSE2 SSE3
(Prescott)
2005?		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 505J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
2005?		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 506 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
2005?		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 2.8A MMX SSE SSE2 SSE3
(Prescott)
2H 2004		775 balls
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 515 MMX SSE SSE2 SSE3
(Prescott)
2005?		775 balls
2933MHz (133x22)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 515J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
2005?		775 balls
2933MHz (133x22)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 519J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
2005?		775 balls
3066MHz (133x23)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 520 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
June 21, 2004 - {$178}		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 520J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November, 2004		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 521 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 530 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
June 21, 2004 - {$218}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 530J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November, 2004		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 531 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.2E MMX SSE SSE2 SSE3
(Prescott)
(EM64T)
2H 2004		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.2F MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T)
2H 2004		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 540 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
June 21, 2004 - {$278}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 540J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November, 2004		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 541 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.4E MMX SSE SSE2 SSE3
(Prescott)
(EM64T)
2H 2004		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.4F MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T)
2H 2004		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 550 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
June 21, 2004 - {$417}		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 550J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November, 2004		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 551 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.6E MMX SSE SSE2 SSE3
(Prescott)
(EM64T)
2H 2004		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.6F MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T)
August 2004		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 560 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading)
June 21, 2004 - {$637}		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 560J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November, 2004		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 561 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.8F MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T)
November 15, 2004 - {$637}		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 570J MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, NX bit)
November 15, 2004 - {$637}		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 571 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 581 MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading, EM64T, NX bit)
[not released]		775 balls
4000MHz (200x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Pentium 4 3.6G MMX SSE SSE2 SSE3
(Tejas)
(Jackson Hyperthreading)
[cancelled]		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
?v		Socket T24KB data (8-way)
16k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Pentium 4 ??? MMX SSE SSE2 SSE3
(Tejas)
(Jackson Hyperthreading)
[cancelled]		775 balls
?MHz (266x?)
(64-bit quad-pumped bus)
?v		Socket T24KB data (8-way)
16k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Pentium 4 ??? MMX SSE SSE2 SSE3
(Nehalem)
(Jackson Hyperthreading)
[cancelled]		775 balls
?MHz (200x?)
(64-bit quad-pumped bus)
?v		Socket T?KB data (8-way)
?k µops trace instruction (8-way)
?MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.065µm process
?mm² die
Pentium 4 630 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
February 21, 2005 - {$224}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 640 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
February 21, 2005 - {$273}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 650 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
February 21, 2005 - {$401}		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 660 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
February 21, 2005 - {$605}		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 662 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit, VT)
November 14, 2005 - {$401}		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 670 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
May 26, 2005 - {$851}		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 672 MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit, VT)
November 14, 2005 - {$605}		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium 4 631 MMX SSE SSE2 SSE3
(Cedar Mill)
(Jackson Hyperthreading, EM64T, NX bit)
February, 2006 - {$178}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket T16KB data (8-way)
12k µops instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		118 million
0.065µm process
?mm² die
Pentium 4 641 MMX SSE SSE2 SSE3
(Cedar Mill)
(Jackson Hyperthreading, EM64T, NX bit)
February, 2006 - {$218}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
?v		Socket T16KB data (8-way)
12k µops instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		118 million
0.065µm process
?mm² die
Pentium 4 651 MMX SSE SSE2 SSE3
(Cedar Mill)
(Jackson Hyperthreading, EM64T, NX bit)
February, 2006 - {$273}		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
?v		Socket T16KB data (8-way)
12k µops instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		118 million
0.065µm process
?mm² die
Pentium 4 661 MMX SSE SSE2 SSE3
(Cedar Mill)
(Jackson Hyperthreading, EM64T, NX bit)
February, 2006 - {$401}		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
?v		Socket T16KB data (8-way)
12k µops instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		118 million
0.065µm process
?mm² die
Pentium 4 671 MMX SSE SSE2 SSE3
(Cedar Mill)
(Jackson Hyperthreading, EM64T, NX bit)
[not released] - {$600}		775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
?v		Socket T16KB data (8-way)
12k µops instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		118 million
0.065µm process
?mm² die
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Pentium D 805 MMX SSE SSE2 SSE3
(Smithfield)
(dual core, EM64T, NX bit)
February, 2006		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* 4GB cacheable		230 million
0.09µm process
206mm² die
Pentium D 820 MMX SSE SSE2 SSE3
(Smithfield)
(dual core, EM64T, NX bit)
May 26, 2005 - {$241}		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* 4GB cacheable		230 million
0.09µm process
206mm² die
Pentium D 830 MMX SSE SSE2 SSE3
(Smithfield)
(dual core, EM64T, NX bit)
May 26, 2005 - {$316}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* 4GB cacheable		230 million
0.09µm process
206mm² die
Pentium D 840 MMX SSE SSE2 SSE3
(Smithfield)
(dual core, EM64T, NX bit)
May 26, 2005 - {$530}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* 4GB cacheable		230 million
0.09µm process
206mm² die
Pentium D 915 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit)
2H 2006		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.3v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 920 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit, VT)
February, 2006 - {$241}		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D-925 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit)
[not released]		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 930 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit, VT)
February, 2006 - {$316}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 940 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit, VT)
February, 2006 - {$423}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 945 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit)
2H 2006		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
?v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 950 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit, VT)
February, 2006 - {$637}		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium D 960 MMX SSE SSE2 SSE3
(Presler)
(dual die, EM64T, NX bit, VT)
2H 2006		775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
1.3v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Pentium 4 Extreme 3.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
November 3, 2003 - {$925}		478 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Pentium 4 Extreme 3.4G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
February 2, 2004 - {$999}		478 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
1.525v or 1.55v or
1.575v or 1.6v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Pentium 4 Extreme 3.4G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
June 21, 2004		775 balls
3400MHz (200x17)
(64-bit quad-pumped bus)
1.6v		Socket T8KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Pentium 4 Extreme 3.46G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
November 1, 2004 - {$999}		775 balls
3466MHz (266x13)
(64-bit quad-pumped bus)
1.6v		Socket T8KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Pentium 4 Extreme 3.73G MMX SSE SSE2 SSE3
(Prescott 2M)
(Jackson Hyperthreading, EM64T, NX bit)
February 21, 2005 - {$999}		775 balls
3733MHz (266x14)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* ?GB cacheable		169 million
0.09µm process
135mm² die
Pentium Extreme 840 MMX SSE SSE2 SSE3
(Smithfield)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
April 18, 2005 - {$999}		775 balls
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* ?GB cacheable		230 million
0.09µm process
206mm² die
Pentium Extreme 955 MMX SSE SSE2 SSE3
(Presler)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
January, 2006 - {$999}		775 balls
3466MHz (266x13)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Pentium Extreme 965 MMX SSE SSE2 SSE3
(Presler)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
March 22, 2006 - {$999}		775 balls
3733MHz (266x14)
(64-bit quad-pumped bus)
1.4v		Socket T2x 16KB data (8-way)
2x 12k µops instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		376 million
0.065µm process
(2) 70mm² die
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Celeron 1.7G MMX SSE SSE2
(Willamette)
May 15, 2002 - {$83}		478 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Celeron 1.8G MMX SSE SSE2
(Willamette)
June 12, 2002 - {$103}		478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Celeron 1.6G MMX SSE SSE2
(Northwood-128)
November, 2004		478 pins
1600MHz (100x8)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 1.8G MMX SSE SSE2
(Northwood-128)
November, 2004		478 pins
1800MHz (100x9)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.0G MMX SSE SSE2
(Northwood-128)
September 18, 2002 - {$103}		478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.1G MMX SSE SSE2
(Northwood-128)
November 20, 2002 - {$89}		478 pins
2100MHz (100x21)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.2G MMX SSE SSE2
(Northwood-128)
November 20, 2002 - {$103}		478 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.3G MMX SSE SSE2
(Northwood-128)
March 31, 2003 - {$117}		478 pins
2300MHz (100x23)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.4G MMX SSE SSE2
(Northwood-128)
March 31, 2003 - {$127}		478 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.5G MMX SSE SSE2
(Northwood-128)
June 25, 2003 - {$89}		478 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.6G MMX SSE SSE2
(Northwood-128)
June 25, 2003 - {$103}		478 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.7G MMX SSE SSE2
(Northwood-128)
September 24, 2003 - {$104}		478 pins
2700MHz (100x27)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.8G MMX SSE SSE2
(Northwood-128)
November 5, 2003 - {$117}		478 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron 2.9G MMX SSE SSE2
(Northwood-128)
[not released]		478 pins
2900MHz (100x29)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v		Socket 4788KB data (4-way)
12k µops trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable		55 million
0.13µm process
131mm² die
Celeron D 310 MMX SSE SSE2 SSE3
(Prescott)
?		478 pins
2133MHz (133x16)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 315 MMX SSE SSE2 SSE3
(Prescott)
2005?		478 pins
2266MHz (133x17)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 320 MMX SSE SSE2 SSE3
(Prescott)
June 24, 2004 - {$69}		478 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 325 MMX SSE SSE2 SSE3
(Prescott)
June 24, 2004 - {$79}		478 pins
2533MHz (133x19)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 330 MMX SSE SSE2 SSE3
(Prescott)
June 24, 2004 - {$89}		478 pins
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 335 MMX SSE SSE2 SSE3
(Prescott)
June 24, 2004 - {$117}		478 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 340 MMX SSE SSE2 SSE3
(Prescott)
September 22, 2004 - {$117}		478 pins
2933MHz (133x22)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 345 MMX SSE SSE2 SSE3
(Prescott)
November 23, 2004 - {$117}		478 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 350 MMX SSE SSE2 SSE3
(Prescott)
June 27, 2005		478 pins
3200MHz (133x24)
(64-bit quad-pumped bus)
1.4v		Socket 47816KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 325J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
September 22, 2004		775 balls
2533MHz (133x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 326 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$73}		775 balls
2533MHz (133x19)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 330J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
September 22, 2004		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 331 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$79}		775 balls
2666MHz (133x20)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 335J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
September 22, 2004		775 balls
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 336 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$89}		775 balls
2800MHz (133x21)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 340J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
September 22, 2004 -{$117}		775 balls
2933MHz (133x22)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 341 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$103}		775 balls
2933MHz (133x22)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 345J MMX SSE SSE2 SSE3
(Prescott)
(NX bit)
November 23, 2004 -{$117}		775 balls
3066MHz (133x23)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 346 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$117}		775 balls
3066MHz (133x23)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 351 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
June 27, 2005 - {$127}		775 balls
3200MHz (133x24)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 355 MMX SSE SSE2 SSE3
(Prescott)
(EM64T, NX bit)
December, 2005		775 balls
3333MHz (133x25)
(64-bit quad-pumped bus)
1.4v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		125 million
0.09µm process
112mm² die
Celeron D 347 MMX SSE SSE2 SSE3
(Cedar Mill)
(EM64T, NX bit)
October 23, 2006 - {$49}		775 balls
3066MHz (133x23)
(64-bit quad-pumped bus)
1.3v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (4-way)
* 4GB cacheable		118 million
0.065µm process
?mm² die
Celeron D 352 MMX SSE SSE2 SSE3
(Cedar Mill)
(EM64T, NX bit)
May, 2006 - {$80}		775 balls
3200MHz (133x24)
(64-bit quad-pumped bus)
1.3v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (4-way)
* 4GB cacheable		118 million
0.065µm process
?mm² die
Celeron D 356 MMX SSE SSE2 SSE3
(Cedar Mill)
(EM64T, NX bit)
May, 2006 - {$90}		775 balls
3333MHz (133x25)
(64-bit quad-pumped bus)
1.3v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (4-way)
* 4GB cacheable		118 million
0.065µm process
?mm² die
Celeron D 360 MMX SSE SSE2 SSE3
(Cedar Mill)
(EM64T, NX bit)
September 24, 2006 - {$89}		775 balls
3466MHz (133x26)
(64-bit quad-pumped bus)
1.3v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (4-way)
* 4GB cacheable		118 million
0.065µm process
?mm² die
Celeron D 365 MMX SSE SSE2 SSE3
(Cedar Mill)
(EM64T, NX bit)
January 21, 2007 - {$69}		775 balls
3600MHz (133x27)
(64-bit quad-pumped bus)
1.3v		Socket T16KB data (8-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (4-way)
* 4GB cacheable		118 million
0.065µm process
?mm² die
VIA
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
? MMX SSE
(CZA)
[cancelled]		478 pins
?MHz (?x?)
?v		Socket 478?KB data (?-way)
?KB instruction (?-way)
?KB on-Die L2
* ?GB cacheable		? million
0.10µm process
?mm² die


Xeon (Socket 603/604)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Xeon 1.4G MMX SSE SSE2
(Foster)
May 21, 2001 - {$268}		603 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Xeon 1.5G MMX SSE SSE2
(Foster)
May 21, 2001 - {$309}		603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Xeon 1.7G MMX SSE SSE2
(Foster)
May 21, 2001 - {$406}		603 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
Xeon 2.0G MMX SSE SSE2
(Foster)
September 25, 2001 - {$615}		603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		42 million
0.18µm process
217mm² die
LV Xeon 1.6G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
September 3, 2002 - {$355}		604 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.3v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
Xeon 1.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
February 25, 2002 - {$251}		603 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
Xeon 2.0A MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
February 25, 2002 - {$417}		603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
LV Xeon 2.0A MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
April, 2003		604 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.3v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
Xeon 2.0B MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
November 18, 2002 - {$198}		604 pins
2000MHz (133x15)
(64-bit quad-pumped bus)
1.5v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
Xeon 2.2G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
February 25, 2002 - {$615}		603 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
146mm² die
Xeon 2.4G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
April 23, 2002 - {$615}		603 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 2.4G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
November 18, 2002 - {$234}		604 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.5v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 2.6G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
September 11, 2002 - {$433}		603 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 2.67G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
November 19, 2002 - {$337}		604 pins
2666MHz (133x20)
(64-bit quad-pumped bus)
1.5v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 2.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
September 11, 2002 - {$562}		603 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 2.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
November 18, 2002 - {$455}		604 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.5v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 3.06G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading)
February 3, 2003 - {$722}		604 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.5v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		55 million
0.13µm process
131mm² die
Xeon 3.06G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
July 14, 2003 - {$690}		604 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.525v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon 3.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
October 6, 2003 - {$851}		604 pins
3200MHz (133x24)
(64-bit quad-pumped bus)
1.525v		Socket 6048KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon 2.8G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
July 28, 2004 - {$209}		604 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 3.0G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
July 28, 2004 - {$316}		604 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 3.2G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
July 28, 2004 - {$455}		604 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 3.4G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
July 28, 2004 - {$690}		604 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 3.6G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
July 28, 2004 - {$851}		604 pins
3600MHz (200x18)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 3.8G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
[not released]		604 pins
3800MHz (200x19)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 4.0G MMX SSE SSE2 SSE3
(Nocona)
(Jackson Hyperthreading, EM64T)
[not released]		604 pins
4000MHz (200x20)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* 64GB cacheable		125 million
0.09µm process
112mm² die
Xeon 2.8G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
February 14, 2005		604 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon LV 3.0G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
September 26, 2005 - {$519}		604 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon 3.0G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
February 14, 2005 - {$316}		604 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon MV 3.2G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
September 26, 2005 - {$487}		604 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon 3.2G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
February 14, 2005 - {$455}		604 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon 3.4G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
February 14, 2005 - {$690}		604 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon 3.6G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
February 14, 2005 - {$851}		604 pins
3600MHz (200x18)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon 3.8G MMX SSE SSE2 SSE3
(Irwindale)
(Jackson Hyperthreading, EM64T, NX bit)
September 26, 2005 - {$851}		604 pins
3800MHz (200x19)
(64-bit quad-pumped bus)
?v		Socket 60416KB data (8-way)
12k µops trace instruction (8-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		133 million
0.09µm process
?mm² die
Xeon ? MMX SSE SSE2 SSE3
(Jayhawk)
(Jackson Hyperthreading)
[cancelled]		? pins
?MHz (166x?)
(64-bit quad-pumped bus)
?v		Socket ?24KB data (?-way)
16k µops trace instruction (8-way)
?MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon DP 2.8G MMX SSE SSE2 SSE3
(Paxville DP)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
October 10, 2005 - {$1043}		604 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		230 million
0.09µm process
206mm² die
Xeon MP 1.4G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading)
March 12, 2002 - {$1177}		603 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
512KB L3 (?-way)
* 64GB cacheable		108 million
0.18µm process
?mm² die
Xeon MP 1.5G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading)
March 12, 2002 - {$1980}		603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
512KB L3 (?-way)
* 64GB cacheable		108 million
0.18µm process
?mm² die
Xeon MP 1.6G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading)
March 12, 2002 - {$3692}		603 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
1MB L3 (?-way)
* 64GB cacheable		108 million
0.18µm process
?mm² die
Xeon MP 1.7G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading)
[not released]		603 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.7v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
256KB on-Die unified L2 (8-way)
1MB L3 (?-way)
* 64GB cacheable		108 million
0.18µm process
?mm² die
Xeon MP 1.5G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
November 4, 2002 - {$1177}		603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 1.9G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
November 4, 2002 - {$1980}		603 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 2.0G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
June 30, 2003 - {$1177}		603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 2.0G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
November 4, 2002 - {$3692}		603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 2.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
March 2, 2004 - {$1177}		603 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
?mm² die
Xeon MP 2.5G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
June 30, 2003 - {$1980}		603 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 2.7G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
March 2, 2004 - {$1980}		603 pins
2700MHz (100x27)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
?mm² die
Xeon MP 2.8G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
June 30, 2003 - {$3692}		603 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.475v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
~230mm² die
Xeon MP 3.0G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading)
March 2, 2004 - {$3692}		603 pins
3000MHz (100x30)
(64-bit quad-pumped bus)
1.5v		Socket 6038KB data (4-way)
12k µops trace instruction (8-way)
512KB on-Die unified L2 (8-way)
4MB on-Die L3 (8-way)
* 64GB cacheable		169 million
0.13µm process
?mm² die
Xeon MP 3.16G MMX SSE SSE2 SSE3
(Cranford)
(Jackson Hyperthreading, EM64T, NX bit)
March 29, 2005 - {$722}		604 pins
3166MHz (166x19)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (?-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon MP 3.66G MMX SSE SSE2 SSE3
(Cranford)
(Jackson Hyperthreading, EM64T, NX bit)
March 29, 2005 - {$963}		604 pins
3666MHz (166x22)
(64-bit quad-pumped bus)
1.4v		Socket 60416KB data (?-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon MP 2.83G MMX SSE SSE2 SSE3
(Potomac)
(Jackson Hyperthreading, EM64T, NX bit)
March 29, 2005 - {$1177}		604 pins
2833MHz (166x17)
(64-bit quad-pumped bus)
1.3875v		Socket 60416KB data (?-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
4MB on-Die L3 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon MP 3.0G MMX SSE SSE2 SSE3
(Potomac)
(Jackson Hyperthreading, EM64T, NX bit)
March 29, 2005 - {$1980}		604 pins
3000MHz (166x18)
(64-bit quad-pumped bus)
1.3875v		Socket 60416KB data (?-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
8MB on-Die L3 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon MP 3.33G MMX SSE SSE2 SSE3
(Potomac)
(Jackson Hyperthreading, EM64T, NX bit)
March 29, 2005 - {$3692}		604 pins
3333MHz (166x20)
(64-bit quad-pumped bus)
1.3875v		Socket 60416KB data (?-way)
12k µops trace instruction (8-way)
1MB on-Die unified L2 (8-way)
8MB on-Die L3 (8-way)
* ?GB cacheable		? million
0.09µm process
?mm² die
Xeon 7020 MMX SSE SSE2 SSE3
(Paxville MP)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
November 1, 2006 - {$1177}		604 pins
2666MHz (166x16)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* ?GB cacheable		338 million
0.09µm process
?mm² die
Xeon 7030 MMX SSE SSE2 SSE3
(Paxville MP)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
November 1, 2006 - {$1980}		604 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
* ?GB cacheable		338 million
0.09µm process
?mm² die
Xeon 7040 MMX SSE SSE2 SSE3
(Paxville MP)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
November 1, 2006 - {$3157}		604 pins
3000MHz (166x18)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		338 million
0.09µm process
?mm² die
Xeon 7041 MMX SSE SSE2 SSE3
(Paxville MP)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
November 1, 2006 - {$3157}		604 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)
* ?GB cacheable		338 million
0.09µm process
?mm² die
Xeon 7110N MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$856}		604 pins
2500MHz (166x15)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7110M MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$856}		604 pins
2600MHz (200x13)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7120N MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1177}		604 pins
3000MHz (166x18)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7120M MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1177}		604 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7130N MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1391}		604 pins
3166MHz (166x19)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7130M MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1391}		604 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7140N MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1980}		604 pins
3333MHz (166x20)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
16MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7140M MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
August 29, 2006 - {$1980}		604 pins
3400MHz (200x17)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
16MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon 7150M MMX SSE SSE2 SSE3
(Tulsa)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
September 27, 2006		604 pins
3500MHz (166x21)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 1MB on-Die unified L2 (8-way)
16MB on-Die shared L3 (16-way)
* ?GB cacheable		1600+ million
0.065µm process
435mm² die
Xeon LV MMX SSE SSE2 SSE3
(Sossaman - embedded)
(dual core, Jackson Hyperthreading, EM64T, NX bit)
March 14, 2006		604 pins
?MHz (166x?)
(64-bit quad-pumped bus)
?v		Socket 6042x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x ?MB on-Die unified L2 (8-way)
* ?GB cacheable		? million
0.065µm process
?mm² die


786 Processor Adapters
Adapter
Manufacturer		Natural
State of Adapter		Goes into
Sockets
Asus CT-479
Adapter
(479-pin Intel Celeron M, Pentium M)		478 pins
2266MHz (133x17.0)
1700MHz (100x17.0)
?v		Socket 478
New Wave NW 478
Adapter
(478-pin Intel Celeron, Pentium 4)		423 pins
2400MHz (100x24.0)
1.75v		Socket 423
PowerLeap P4/N
Adapter
(478-pin Intel Celeron, Pentium 4)		423 pins
2800MHz (100x28.0)
?v		Socket 423
PowerLeap P4P
Adapter
(478-pin Intel Prescott)		478 pins
3200MHz (133x24.0)
?v		Socket 478


Notes:
Current URL: http://www.pchardwarelinks.com/786.htm
Designed by: Chris Hare
© 1997-Present by Chris Hare
Legal Stuff
Last Updated: March/29/2010