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486 Processor Pinouts

169 pins - 17x17 Pin Grid Array - Zero Insertion Force socket or Low Insertion Force socket.
Bottom view of the processor (pin side). Pin One is in the lower left corner.


    1   2   3   4   5   6   7   8   9   10  11  12  13  14  15  16  17
  |-------------------------------------------------------------------|
S | o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
  |                                                                   |
R | o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
  |                                                                   |
Q | o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
  |                -----------------------------------                |
P | o   o   o    /                                     \    o   o   o |
  |            /                                         \            |
N | o   o   o |                                           | o   o   o |
  |           |                                           |           |
M | o   o   o |                                           | o   o   o |
  |           |                                           |           |
L | o   o   o |                                           | o   o   o |
  |           |                                           |           |
K | o   o   o |                                           | o   o   o |
  |           |                BOTTOM VIEW                |           |
J | o   o   o |                (pin side)                 | o   o   o |
  |           |                                           |           |
H | o   o   o |                                           | o   o   o |
  |           |                                           |           |
G | o   o   o |                                           | o   o   o |
  |           |                                           |           |
F | o   o   o |                                           | o   o   o |
  |           |                                           |           |
E | o   o   o |                                           | o   o   o |
  |            \                                         /            |
D | o   o   o   o\                                     /    o   o   o |
  |                -----------------------------------                |
C | o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
  |                                                                   |
B | o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
  |                                                                   |
A \ o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o   o |
   \------------------------------------------------------------------|
    1   2   3   4   5   6   7   8   9   10  11  12  13  14  15  16  17

The chart is available online in HTML format: 486PIN2.HTM. Be aware that it is a large chart and may take a few seconds to load.

The chips included are:

Intel 486SX (P23)
Intel 486SX SL-enhanced (P23S)
Intel 487SX Math Coprocessor (P23N)
Intel 486 OverDrive (ODP - P23T)
Intel 486 OverDrive Replacement (ODPR - P4T)
Intel 486DX (P4)
Intel 486DX SL-enhanced (P4S)
Intel 486DX2 (P24)
Intel 486DX2 SL-enhanced (P24S)
Intel 486DX4 SL-enhanced low voltage (P24C)
Intel 486DX2 SL-enhanced write-back enhanced (P24D)
IBM 486DX SMM
IBM 486DX low voltage SMM
IBM 486DX2 SMM
IBM 486DX2 low voltage SMM
IBM 486DX4 SMM
IBM 486DX4 write-back enhanced SMM
IBM 5x86C SMM
AMD 486DX2 low voltage (no SMM)
AMD 486DX2 write-back enhanced SMM
AMD 486DX4 low voltage (no SMM)
AMD 486DX4 write-back enhanced SMM
AMD 5x86 SMM
SGS-Thomson 486DX SMM
SGS-Thomson 486DX2 SMM
SGS-Thomson 486DX2 low voltage SMM
SGS-Thomson 5x86 SMM
Cyrix 5x86 SMM

This list is not comprehensive. Many chips are not listed here including AMD, IBM, Texas Instruments, and especially Cyrix. The Cyrix, IBM, and TI chips often share very similar pinouts though that doesn't mean that all three manufacturers produced all of each other's chips.

Only 486 processors are listed here. The Cyrix, IBM, and Texas Instruments 486DLC chips are 386/486 hybrids with a 386 pinout, and are not listed. The Intel Pentium OverDrive for 486 (P24T) is not listed because of its extra row of pins. For the P24T pinout, see Intel's Pentium OverDrive datasheet.

As of March 9, 1999, pinouts for the 468DX ODP and ODPR processors have been added. Former ODP and ODPR processors have been re-named to ODP-S and ODPR-S to differentiate them from the non-SL-enhanced ODP and ODPR. And pins A3, A14, B14, B16, and C11 have been corrected on the ODPR-S.
As of March 17, 1999, The C12 pin on the non-SL enhanced Intel OverDrive (ODPR) was corrected from SMIACT# to NC.
As of January 3, 2000, the Cyrix 5x86 has been added.
As of March 2, 2001, pins A15 and B15 have been corrected on the Intel 486SX and SL enhanced 486SX processors.

Chart Abbreviations

-- - No pin
INC - Internal No Connect
NC - No Connect
Res - Reserved
Vcc - Voltage supply
Vss - Voltage ground
The IBM, Cyrix, and Texas Instruments 486 chips share similar pinouts.
The UMC U5D and U5S are clones of the Intel 486DX and 486SX, and share the same pinouts.

Common Pin Designations

`A2 - A31`	Address pins.
`A20M#`	Address bit 20 Mask pin.
`ADS#`	Address Status.
`AHOLD`	Address Hold.
`BE0 - BE3#`	Byte Enable pins.
`BLAST#`	Burst Last.
`BOFF#`	Back Off input.
`BRDY#`	Burst Ready.
`BRDYC#`	Cache Burst Ready.
`BREQ`	Bus Request.
`BS8#`	Bus Size 8.
`BS16#`	Bus Size 16.
`CACHE#`	Cache.
`CLK`	Clock input. Provides fundamental timing for the processor.
`CLKMUL`	Clock Multiplier pin (Bus Frequency). Usually 2.0x or 3.0x, though it can be 2.5x or 4.0x, depending on the chip.
`D0 - D31`	Data pins.
`D/C#`	Data/Code. Primary bus cycle definition pin.
`DP0 - DP3`	Data Parity pins.
`EADS#`	External Address Strobe.
`FERR#`	Floating Point Error.
`FLUSH#`	Cache Flush.
`HITM#`	Hit to a Modified line.
`HLDA`	Hold Acknowledge.
`HOLD`	Bus Hold request.
`IGNNE#`	Ignore Numeric Error.
`INTR`	Maskable Interrupt.
`INV`	Invalidate.
`INVAL`	Invalidate.
`KEN#`	Cache Enable.
`KEY`	Key pin. Non-functional pin to prevent incorrect CPU insertion.
`LOCK#`	Bus Lock.
`M/IO#`	Memory/Input-Output. Primary bus cycle definition pin.
`MP#`	Math-coprocessor Present. When pulled low, the processor enters a powered-down tristate mode, allowing the math-coprocessor to take control.
`NMI`	Non-Maskable Interrupt.
`PCD`	Page Cache Disable.
`PCHK#`	Parity Status.
`PLOCK#`	Pseudo-Lock.
`PWT`	Page Write-Through.
`RDY#`	Non-burst Ready.
`RESET`	Reset.
`RPLSET0`	?.
`RPLSET1`	?.
`RPLVAL#`	?.
`SMADS#`	System Management Interrupt Address Strobe.
`SMI#`	System Management Interrupt. Allows processor to enter system management mode.
`SMIACT#`	System Management Interrupt Active. Indicates that processor is in system management mode.
`SRESET`	Soft Reset.
`STPCLK#`	Stop Clock.
`SUSP#`	Suspend. Same as STPCLK#.
`SUSPA#`	?.
`TCK`	Test Clock.
`TDI`	Test Data Input.
`TDO`	Test Data Output.
`TEST`	Test pin.
`TMS`	Test Mode Select.
`UP#`	Upgrade Present. When pulled low, the processor enters a powered-down tristate mode, allowing an upgrade processor to take control.
`VOLDET`	Voltage Detect.
`WB/WT#`	Write-Back / Write-Through.
`WM_RST`	Warm Reset.
`W/R`	Write / Read.

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Last Updated: March/2/2001